1. Field of the Invention
The present invention relates to a dry etching technique, and more particularly to an improved dry etching method of a multilayer film with regard to a semiconductor device including a metallic layer and a polysilicon layer.
2. Description of the Background Art
As semiconductor devices are highly integrated, a high speed LSI (Large Scale Integrated circuit) is strongly required. In order to satisfy a high speed semiconductor device, an inner connection resistance should be decreased, and accordingly a significant interest is directed to a metallic gate to reduce the inner connection resistance of a semiconductor device. Most of all, a dual structure inner connection is now under generalization, wherein a metallic layer or a metallic silicide layer is deposited on a polysilicon layer. In recent years, studies have been made with respect to an inner connection structure by use of a multilayer including a diffusion barrier layer between the polysilicon layer and the metallic layer. In particular, electrical characteristics in relation to an inner connection structure including a tungsten, molybdenum or silicide layer on the polysilicon layer have been explained. However, although there are many of theses dealing with respective etching methods of the polysilicon layer, metallic layer or silicide layer, a further systematic study is required with respect to etching methods of a multilayer including a polysilicon/metallic layer or a polysilicon/metallic-silicide layer.
An etching process of a stacked structure including a polysilicon/metallic layer or a polysilicon/metallic-silicide layer is as follows.
U.S. Pat. No. 5,295,923 discloses an etching method of a multilayer in which either of tungsten, molybdenum, tungsten silicide, molybdenum suicide serving as a metallic layer or a metallic silicide layer is stacked on a polysilicon layer. That is, the metallic or metallic silicide layer deposited on the polysilicon layer is etched in a first step. The first etching step employs an anisotropic etching method by use of a compound gas mixed by a fluorine gas such as SF.sub.6, NF.sub.3, and a gas selected from HCl, HBr, Cl.sub.2, Br.sub.2 and CCl.sub.4. Then, according to a second step, the polysilicon layer is etched under an anisotropic etching method, by use of a compound gas mixed by a fluorine gas such as SF.sub.6, NF.sub.3, and a gas selected from SiCl.sub.4, fluorine gas, N.sub.2, O.sub.2 and CO.
In a method for etching a multilayer having a stack structure of polysilicon/nitro-titanium(TiN)/tungsten(W), a W/TiN layer is etched by use of a compound gas mixed by SF.sub.6 gas and Cl.sub.2 gas in the first step, and the polysilicon layer is etched by use of HBr gas in the second step as disclosed in IEDM proceedings p447-450.
As disclosed in U.S. Pat. No. 5,160,407 which deals with an etching method with regard to a multilayer of polysilicon/titanium-silicide(TiSi.sub.x) or polysilicon/tantalum-silicide(TaSi.sub.x) structure. Therein, TiSi.sub.x or TaSi.sub.x is etched only by Cl.sub.2 gas, and polysilicon is etched only by HBr gas.
FIG. 1 is a schematic cross-sectional view of a semiconductor substrate in which a polysilicon/metallic multilayer is etched using a conventional etching method.
As shown therein, on a semiconductor substrate 1 there is formed a polysilicon oxide layer 2. A polysilicon pattern 3 is formed on the silicon oxide layer 2, and a metallic pattern 4a or a silicide pattern 4a and a mask pattern 5 are sequentially formed on the polysilicon pattern 3. Between the pattern stacks and on the silicon oxide layer 2 there are left residues 6 after the etching.
FIG. 2 is a schematic cross-sectional view of a semiconductor substrate according to a conventional etching method, wherein a chlorine gas is employed to remove the leftover residues 6 formed on the silicon oxide layer 2 of FIG. 1. As shown therein, a polysilicon pattern 3a is formed by an undercut process.
FIG. 3 is a schematic cross-sectional view illustrating another example of a semiconductor substrate, wherein a polysilicon/metallic multilayer is etched by a conventional etching method. As shown therein, on a semiconductor substrate 1 there is formed a silicon oxide layer 2, and a polysilicon layer 3b, a metallic layer 4a or a metallic silicide pattern 4a, and a mask pattern 5 are sequentially formed on the silicon oxide layer 2. Therein, the polysilicon layer 3b is not completely etched and part of the silicon oxide layer 2 is left over after the etching.
The residues or the partially leftover polysilicon layer after the etching result from the following reasons. That is, in order to obtain vertical side walls of the metallic layer of the metallic silicide layer, an etching gas is mixed with a fluorine gas such as Ar, He, and a passivation gas such as O.sub.2, N.sub.2, CO for protecting sidewalls of etching targets. Here, the fluorine gas or passivation gas is reacted to metal and generates a non-volatile remainder, so that there are left over etch-blocking materials on the polysilicon layer and accordingly the leftover etch-blocking materials prohibit a subsequent etching of the polysilicon layer, thereby causing an undesired etch stoppage or generating a significant amount of residues.
Also, as shown in FIGS. 1 and 2, there may occur an undercut between a metallic layer or a metallic silicide layer as an upper layer and a polysilicon layer as a lower layer.
Further, when there is employed a chlorine compound gas to remove the etch blocking layer or the residues, a critical undercut may be incurred, thereby deteriorating characteristics of the semiconductor device.